1. Field of the Invention
The present invention relates to a technical field of processor and, more particularly, to a processor and method by using parity check to switch instruction modes in a computer device.
2. Description of Related Art
Typically, a processor is provided with 32-bit/16-bit instruction modes and capable of switching between the two modes to save required memory for storing programming codes. U.S. Pat. No. 5,758,115 granted to Nevill and Edward Colles for an “Interoperability with multiple instruction sets” uses T bit of a program counter (PC) to determine whether the processor is in 32-bit or 16-bit instruction mode and uses a branch instruction to change values of the T bit of the program counter. The instruction modes are switched as shown in FIG. 1. When the branch instruction 220 is performed after the data processing 210 to branch a program flow to a start address Badd(1) that is stored with a 16-bit instruction so as to execute the 16-bit instruction, the T bit is switched by +1 to inform the processor to be in the 16-bit instruction mode for the data processing 230. The branch instruction 240 is performed after the data processing 230 to branch the program flow to address Badd(2) that is stored with a 32-bit instruction to execute the 32-bit instruction for the data processing 250.
As to the aforementioned problem, U.S. Pat. No. 6,209,079B1 granted to Otani, et al. for a “Processor for executing instruction codes of two different lengths and device for inputting the instruction codes” has provided a solution by applying the most significant bit (MSB) of an instruction code to determine whether the processor is in 32-bit or 16-bit instruction mode. As shown in FIG. 2, the 32-bit word contains a 32-bit instruction if the MSB on 32-bit boundary is ‘1’ and two 16-bit instructions if the MSB on 32-bit boundary is ‘0’. Two 16-bit instructions are performed sequentially if the MSB of 16-bit instruction B is ‘0’. Two 16-bit instructions are performed in parallel if the MSB of 16-bit instruction B is ‘1’. Such an instruction mode switch is used in the processors of M32R series. In this case, the 32-bit and 16-bit instructions can be stored in the same block to increase code density. However, when a branch or jump instruction is performed, it needs to be dealt careful to avoid jumping to the last half portion of a 32-bit instruction. Because the last half portion of a 32-bit instruction is not executable, it may cause unpredictable error. Therefore, the jump address requires to be limited to a word boundary or 32-bit boundary. The return addresses for branch-and-link and jump-and-link instructions also require to be limited to a word boundary or 32-bit boundary. Such a limitation adds inconvenience in use. In addition, there is no error tolerance designed for the above processor in executing the branch or jump instruction. That is, when the processor produces a wrong jump address due to a hardware problem or external interference, the processor may lead to system halt. Therefore, the conventional 32-bit/16-bit instruction mode switching still encounters many problems, and thus it is desirable to provide an improved processor and method to mitigate and/or obviate the aforementioned problems.